IEEE Secure Development Conference

October 18 - 20, 2023
Georgia Tech Hotel and Conference Center
Atlanta, GA

Sponsored by the IEEE Computer Society Technical Committee on Security and Privacy



Posted on: September 27th, 2023 by SecDev

Jason Fung
Intel Corp.

Mega Chips, Mega Challenges: The Quest for Trustworthy Hardware

Bio: Jason M. Fung is the Director of Offensive Security Research and Academic Research Engagement at Intel Product Assurance and Security (IPAS). He oversees emerging threat research of key technologies that power Intel’s edge, communication and data center products. He also leads academic and industry collaborations that advance best practices in product security assurance for the semiconductor industry. Recent contributions include the creation of the community-driven Hardware Common Weakness Enumeration (CWE) (, the industry-first Pre-Si Hardware Capture-the-Flag Competitions (, and the Intel Research Experience for Undergraduates Program focusing on nurturing future security leaders in collaboration with Princeton, Georgia Tech and UNC. He is a founding member of the CAPEC/CWE Advisory Board. Over his 25-year tenure at Intel, Jason has held various roles encompassing architecture and performance, verification automation, research and pathfinding, security assurance and consultation, and engineering management.

Abstract: Modern commercial-grade Silicon-on-Chips (SoC) are meticulously crafted with hundreds of unique Intellectual Property (IP) building blocks, each featuring varying functionalities and complexities. These IPs, ranging from general-purpose microprocessors to purpose-built workload accelerators, are sourced from in-house designs and third-party solution providers, supporting a wide array of interfaces and interconnects. Advancements in manufacturing and 3D packaging technologies have ushered in a new era of chip design, moving from traditional monolithic processors to disaggregated chiplet architecture. Separate tiles, responsible for specific functionalities like compute, I/O, and graphics, are interconnected and stacked die-to-die to create mega chips with over 100 billion transistors. Moore’s Law continues to be in effect, doubling the number of transistors per device every 2 years. The rise of Machine Learning and Generative AI will further drive technological innovations that demand chips to be more complex than ever.

Despite these technological advancements, the Electronic Design Automation (EDA) industry has struggled to keep pace with the evolving demands of hardware engineers. Whether tasked with developing secure technologies for mission-critical applications or trustworthy solutions for everyday life, engineers often find themselves searching for the right tools in their arsenal. To meet these challenges, there is an imperative need for further innovation in modernizing tools and methodologies, with a strong focus on security assurance.

In this talk, we will share our journey towards revolutionizing hardware security assurance, encompassing technology advancements, open standards, research investments, community engagement, and talent development. We will delve into the various technological challenges the industry faces, explore research opportunities, and discuss the crucial role that experts from diverse disciplines, including the software security community, can play in shaping the future of hardware security.